The K5 was AMD's first x86 processor developed entirely in-house, introduced in March 1996. Its primary competition was Intel's Pentium microprocessor range. Although it was originally scheduled for launch in 1995, due to design issues, it was delayed until 1996. AMD as a company was not as mature as Intel regarding microprocessor design, thus a lot of deadlines were missed and there was a lack of manufacturing expertise in scaling designs. The K5's was an ambitious design, closer to a Pentium Pro than a Pentium regarding technical solutions and internal architecture. However, the final product was regrettably closer to the Pentium regarding performance.
Technical details:
The K5 was based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating point unit. The branch target buffer was four times the size of the Pentium's and register renaming improved parallel performance of the pipelines. The chips speculative execution of instructions reduced pipeline stall. It touted an instruction cache of 16 KiB, which was double that of the Pentium. Further, the primary cache was a "4-way" set associative, instead of the Pentium's "2-way" set. The K5 lacked MMX instructions, which Intel started offering in its Pentium MMX processors that were launched in early 1997. Compared to the Pentium the K5's floating point unit had around 10% less performance clock for clock.
Performance
The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation had its issues. The low clock rates were, in part, due to AMD's limitations as a "cutting edge" manufacturing company at the time, in part due to the design itself (many levels of logic, thus slowing it down). Having a branch prediction unit four times the size of the Pentium, yet reportedly not delivering superior performance is an example of how the actual implementation fell short of the projects goals. Additionally, while the K5's floating point performance was better than that of the Cyrix 6x86, it was weaker than that of the Pentium. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed.
Technical details:
The K5 was based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating point unit. The branch target buffer was four times the size of the Pentium's and register renaming improved parallel performance of the pipelines. The chips speculative execution of instructions reduced pipeline stall. It touted an instruction cache of 16 KiB, which was double that of the Pentium. Further, the primary cache was a "4-way" set associative, instead of the Pentium's "2-way" set. The K5 lacked MMX instructions, which Intel started offering in its Pentium MMX processors that were launched in early 1997. Compared to the Pentium the K5's floating point unit had around 10% less performance clock for clock.
Performance
The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation had its issues. The low clock rates were, in part, due to AMD's limitations as a "cutting edge" manufacturing company at the time, in part due to the design itself (many levels of logic, thus slowing it down). Having a branch prediction unit four times the size of the Pentium, yet reportedly not delivering superior performance is an example of how the actual implementation fell short of the projects goals. Additionally, while the K5's floating point performance was better than that of the Cyrix 6x86, it was weaker than that of the Pentium. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed.